Parameterized Block-Based Non-Gaussian Variational Gate Timing Analysis

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by σTA) is becoming unavoidable. In this paper, two new approaches for doing statistical gate timing analysis for Gaussian and non-Gaussian sources of variation in block-based σTA are presented. To start, a variational RC-π load is approximated by using a canonical first-order model. Next, an accurate variational gate timing analysis (VGTA) technique, which accounts for variational RC-π loads, statistical input transitions, and a variation-aware gate library, is introduced. The proposed method relies on a novel static effective capacitance calculation method and its variational form. Experimental results demonstrate that VGTA exhibits an average error of only 4% for gate delay and output transition time with respect to the Monte Carlo simulation with 10 samples. Next, a more efficient variational gate timing analysis (called F-VGTA) based on a single-iteration variational effective capacitance calculation is presented. Experimental results show F-VGTA achieves an average error of 7% for gate delay and output slew time with respect to the Monte Carlo simulation with 10 samples, but with runtimes that are about two times faster than VGTA. * This paper combines and extends results of our works, which were presented at the 2005 International Conference on Computer Design and the 2006 Asia-South Pacific Design Automation Conference.